1. Field of the Invention
The present invention relates to a process for forming so-called "direct contacts" in integrated devices.
2. Discussion of the Related Art
In MOS and in CMOS integrated circuits the need of establishing an electrical connection between a drain or source diffusion (e.g., between an output node of a logic gate) and a polysilicon gate structure (e.g., an input node of another logic gate of the integrated circuit) is encountered often.
This connection may of course be made by a customary metal connection, but this solution is rather burdensome in terms of occupied area, because it requires the formation of two contact windows through a dielectric layer and of the relative contact "heads" or plugs. Moreover, the use of a patterned metal segment for establishing the connection restricts the room for other connections by constituting a "forbidden" zone that must eventually be avoided by going around it or by over-passing it through an upper level of metallization.
The area requirement for these connections is particularly penalizing in the case of certain integrated circuits, like SRAMs, wherein maximum compactness is desired.
A preferable alternative consists in forming a so-called direct contact between a patterned polysilicon gate structure and a certain source or drain area of the semiconductor, without using an overlaying metal layer for making the connection.
A direct contact must ensure the formation of a good ohmic contact between a film or layer of conducting material, commonly an n-doped polycrystalline silicon (polysilicon), and the semiconducting substrate, commonly a semiconducting silicon monocrystal. An essential requisite to achieve this is to ensure the removal of any residue of oxide in the contact area, including the so-called "native" oxide, i.e., a thin layer of oxide which spontaneously forms on the surface of a silicon monocrystal when exposed to air at room temperature in the contact area. Normally, for masking a direct contact, it is necessary to etch through a suitable mask, a dielectric layer (a gate oxide layer) in the area where the contact must be established. Moreover it is necessary to ensure the removal of any native oxide immediately before depositing the contacting layer, commonly of polysilicon. Removal of a native oxide film is normally done by washing the wafer in a solution containing chemical agents having a particular aggressiveness toward the oxide, such as for example hydrofluoric acid (HF).
The drawback of this type of washing operation for removing the film of native oxide is represented by the fact that the gate oxide layer that is present on the remaining portions of the active areas is also subjected to a hardly controllable and intrinsically nonuniform etching, which may cause an intolerable spread of the electrical parameters of the integrated devices. These problems are already serious in present-day CMOS processes and will become even more so in processes of future generation because of the tendency to utilize a gate oxide layer having an extremely small thickness (less than 20 nm).
Special techniques for removing the film of native oxide from contact areas have been reported. One of these techniques employs a special dry-cleaning machine that uses anhydrous HF instead of a solution thereof. These machines, under optimized working conditions, are reportedly capable of etching the native oxide which forms spontaneously on contact areas in a sufficiently selective manner versus the gate oxide layer that by contrast has been thermally grown. Reportedly this technique has the drawback of being very sensitive to the real working conditions and this may lead to a poor reproducibility in production.
In a prior European patent application, No. 92830540.8, filed on September 30, 1992 by the same applicant of the present invention, an improved method is described for forming direct contacts that consists in defining and "opening" a contact area through a first layer of conducting material, typically of polycrystalline silicon or briefly of polysilicon, which is purposely deposited beforehand over a dielectric gate layer present on active areas of the wafer.
The presence of a protective first layer of polysilicon permits to remove the film of native oxide from the contact area on the surface of the monocrystalline silicon substrate under conditions of practically absolute protection of the gate dielectric present on the other portions of active area.
A second layer of adequate thickness of polysilicon is eventually deposited in direct contact with the substrate in the freshly cleaned contact area and over said first layer.
Even though this new method overcomes some specific difficulties of the methods of the prior art it retains a critical aspect. According to such a method, schematically depicted in FIGS. 1A and 1B, as well as in previously known methods, in order to guarantee electrical continuity between the contacting polycrystalline silicon 1 and the region 2 of the semiconducting substrate, it is necessary that the aperture A of the mask used for defining the direct contact area be wider than the patterned strip of polycrystalline silicon 1, as depicted in FIG. 1A. Otherwise, the patterned polysilicon 1, by laying over a gate oxide layer beyond the definition border of the direct contact area, would unduly constitute a gate and therefore could eventually interrupt electrical continuity in the semiconductor.
Within such a wider definition area A of a direct contact, the gate dielectric (oxide) is removed at the end of the etching that is conducted initially through the thickness of a first protective layer of deposited polycrystalline silicon, thus pre-arranging the so defined direct contact area to receive a second deposited layer of polycrystalline silicon, or a single polycrystalline silicon layer, in the case of processes known before the invention described in said prior European patent application. The subsequent patterning step of the polycrystalline silicon through a mask defining the gate structures of transistors, necessarily implies also the carrying out of a certain over-etching to eliminate residues of polycrystalline silicon along "discontinuities" of the surface profile as well as for the necessity to account for nonuniformities of the thickness of the deposited polycrystalline silicon layer. This need would be intrinsically more pronounced in the case of the method of said prior patent application because of the two-step deposition process. Customarily, for a thickness of deposited polysilicon of about 0.4 .mu.m, it is necessary to perform the etching for an "equivalent" apparent thickness of about 0.6 .mu.m. Such an over-etching that generally does not represent a problem, because the etching is "arrested" by the gate oxide or by the field oxide present under the polycrystalline silicon layer, becomes a problem within direct contacts' definition areas because the gate oxide is no longer present within said relatively wider definition area. In these portions of the definition area of a direct contact the over-etching of the polycrystalline silicon inevitably produces also a certain etching of the semiconducting silicon substrate 3, as evidenced in the schematic cross section of 1B. The etching of the silicon substrate 3 can hardly be prevented because it is not possible to obtain a sufficient etch selectivity between polycrystalline silicon and monocrystalline silicon.
Such an undesirable cutting of the silicon substrate in the area of definition of a direct contact is proportionally greater when the thickness of the polycrystalline silicon layer over this area is smaller than the thickness of the polycrystalline silicon layer over the rest of the surface, as in the case of the method of the above-noted prior patent application wherein the thickness of the layer of polycrystalline silicon within the area of definition of a direct contact corresponds to the thickness of only the second deposited layer. As a consequence, a marked etching of the monocrystalline silicon substrate occurs in this area and this may affect the functionality of the integrated circuit if it is not sufficiently controlled. In view of the fact that the doping of drain and source regions is performed by ion implantation, i.e., under intrinsically anisotropic conditions, it may happen that, in presence of an excessive cutting of the semiconducting silicon substrate and of relatively shallow junction depths (diffusions) typical of sub-micron processes, the implanted and diffused region 2b at the bottom of the etched zone may not be electrically connected to the implanted and diffused region 2 of the rest of the region to be contacted.
An object of the present invention is that of overcoming this problem.